This invention relates in general to a selective call receiver having a frequency synthesizer for changing receive frequencies in order to receive a paging signal. This invention more specifically relates to varying characteristics of the receiver in response to the receive frequency.
A paging receiver which receives a paging signal on one of a plurality of receive frequency channels, needs to switch between receive frequency channels. However, the lock time of a frequency synthesizer having a phase lock loop (PLL) may vary depending upon the differences in frequency between two channels. It is desirable to provide a constant lock time when switching channels regardless of the differences in frequency. Furthermore, it is desirable to lock to another channel very rapidly in one instance while the lock time may not be critical in another instance. Thus it is desirable to vary the characteristics of a selective call receiver in order to provide for a desired lock time.
The loop filter of the PLL also effects the noise level of the synthesized frequency used within a superheterodyne receiver, the noise level effects the selectivity of the receiver. Different applications of paging receivers or different channels upon which paging receivers receive paging signals may require differing selectivity performance. Thus it is desirable to adjust the loop bandwidth of a PLL in order to provide a desired level of selectivity performance.
During the reception process, a demodulated signal has a DC component and an AC component upon which the paging signal is included. The DC component is removed in order to digitize the AC component. A complex circuit is used to determine and extract the DC component, such a circuit is shown in U.S. Pat. No. 4,631,737 to Davis et al. It is desirable to disable this circuit while the PLL is acquiring lock.